1. Field of the Invention
The present invention generally relates to a reset signal generating circuit, in particular, to a power-low reset circuit.
2. Description of Related Art
In designing an electronic circuit, a reset mechanism is usually added in the electronic circuit to restore it to an initial status when needed. Especially, every component is under an uncertain status at an initial moment of turning on a power source so that it is necessary to reset the circuit, thus restoring every component in the circuit to its initial status.
Accordingly, a circuit for generating a reset signal is required to reset all components in the circuit to the initial status. FIG. 1A is a conventional power-on reset circuit. Referring to FIG. 1A, stored charges on a capacitor 112 will discharge via a resistance 111 before the power source is started to turn on, hence, the N-type transistor 114 will be at a cut-off status when the power source is started to turn on so that the power-on reset circuit in FIG. 1A may generate a reset signal with a high electrical potential by passing a current through the resistance 113 and the buffer 115. Next, by passing a current through a resistance 110, the capacitor 112 is charged to a voltage level exceeding a threshold voltage of the transistor 114. The electrical potentials of the capacitor 112 and the transistor 114 are the same because they are connected in parallel, thus reversing the transistor 114 to an “on” status. Therefore, the transistor 114 will disable the reset signal (RST).
The laid-open U.S. publication No. 2001/0028263 A1 filed on Oct. 11th, 2001, entitled “Power on reset circuit”, discloses a power-on reset circuit shown in FIG. 1B. In the power-on reset circuit, a current passing through a transistor 121 is shunted to the capacitor 123 and the transistor 122, thereby lengthening the charging time of the capacitor 123. Eventually, a charged electrical potential of the capacitor 123 allow an inverter 124 to be reversed and thus generating a power-on reset effect. However, a current passing through the transistor 122 must be precisely controlled because the current is too small to keep the reset signal for a sufficient time and is too large to charge the capacitor to a voltage level required to reverse the inverter 124. Besides, a process for charging and discharging the capacitor will consume more current.
FIG. 1C shows a power-on reset circuit disclosed in U.S. Pat. No. 6,388,479, entitled “Oscillator based power-on-reset circuit,” (filed on Mar. 22, 2000 and granted on May 14, 2002). Referring to FIG. 1C, in a power-on-reset circuit 130, the clock signal outputted from an oscillator 131 directly passes through the low-pass filter of the transistor 132 and the capacitor 133 to affect an electrical potential stored in the capacitor 133. The power-on-reset effect can be generated after the electrical potential of the capacitor 133 exceeds the threshold point for reversing an inverter 134's status. However, the RC time constant of the conducting resistance of the transistor 132 and the capacitor 133 is required to be larger than the pulse-width of the clock signal of the oscillator 131, otherwise, the power-on-reset circuit can not achieve the reset action. Moreover, the reset signal outputted from the power-on-reset circuit 130 will oscillate.
FIG. 1D shows a power-on reset circuit disclosed in U.S. Pat. No. 5,386,152, entitled “Power-on-reset circuit responsive to a clock signal,” (filed on Mar. 17, 1993 and granted on Jan. 31, 1995). Referring to FIG. 1D, in the power-on reset circuit 140, since the charge/discharge signal is acquired by employing a positive source and a negative source of a clock amplifier to trigger a differentiator circuit, a diode protection circuit is needed to prevent an over large reverse signal from reversely entering the circuit via a ground line. Therefore, such a circuit easily induces an unnecessary interfering signal and also generates a signal with a voltage lower than the ground voltage. Moreover, the reset signal outputted from the power-on-reset circuit 130 will oscillate.
However, when a power source voltage VDD drops for some reasons (not while turning off the power source), an unpredictable status of a system will occur due to an over low voltage. After the power source voltage VDD is restored to a normal operating voltage, the system can not normally operate because of its internal confused signals. Accordingly, it is necessarily that the power-on reset circuit sends a reset signal for resetting the system to a start status at an appropriate time after the power source voltage VDD is restored to the normal operating voltage from a dropped voltage. Most prior arts described above can not re-send the reset signal after the power source voltage VDD is dropped and then restored to the normal operating voltage.